1. Field of the Invention
The present invention relates to a semiconductor storage device, and in particular, to a semiconductor storage device with a structure where memory cell arrays are laminated on the semiconductor substrate.
2. Description of the Related Art
Resistive memory has attracted increased attention as a likely candidate for replacing flash memory. As described herein, it is assumed that the resistive memory devices include Resistive RAM (ReRAM), in a narrow sense, that uses a transition metal oxide as a recording layer and stores its resistance states in a non-volatile manner, as well as Phase Change RAM (PCRAM) that uses chalcogenide, etc., as a recording layer to utilize the resistance information of crystalline states (conductors) and amorphous states (insulators).
It is known that the variable resistance elements in resistive memory have two modes of operation. One is to set a high resistance state and a low resistance state by switching the polarity of the applied voltage, which is referred to as “bipolar type”. The other enables the setting of a high resistance state and a low resistance state by controlling the voltage values and the voltage application time, without switching the polarity of the applied voltage, which is referred to as “unipolar type”.
To achieve high-density memory cell arrays, the unipolar type is preferable. This is because that the unipolar type solution enables, without transistors, cell arrays to be configured by superposing variable resistance elements and rectifier elements, such as diodes, on respective intersections between bit lines and word lines. Moreover, large capacity may be achieved without an increase in cell array area by arranging such memory cell arrays laminated in a three-dimensional manner (see Japanese National Publication No. 2005-522045).
For unipolar-type ReRAM, data is written to a memory cell by applying, for a short period of time, a certain voltage to a variable resistance element. As a result, the variable resistance element changes from a high resistance state to a low resistance state. The operation of changing a variable resistance element from a high resistance state to a low resistance state is hereinafter referred to as the “set operation”. On the other hand, data is erased from a memory cell MC by applying, for a long period of time, a certain voltage that is lower than that applied in the set operation to a variable resistance element in its low resistance state after the set operation. As a result, the variable resistance element changes from a low resistance state to a high resistance state. The operation of changing a variable resistance element from a low resistance state to a high resistance state is hereinafter referred to as the “reset operation”.
It is necessary to flow a current of several μA to change a selected memory cell from the low resistance state to the high resistance state in the reset operation. Although the current flows to a selected word line and a selected bit line, since a wiring resistance of these wirings is about several tens of KΩ, a voltage drop (IR drop) due to the wiring resistance cannot be ignored. When a voltage drop due to a parasitic resistance of overall paths to which a reset current flows is taken into consideration, it is necessary to apply a voltage, which is larger than a certain voltage necessary for the reset operation of the variable resistor element, to a selected bit line to which the selected memory cell is connected. With this operation, even if the voltage drop due to the parasitic resistance occurs, a desired voltage and the reset current can be supplied to the selected memory cell.
When the selected memory cell is changed from the low resistance state to the high resistance state by the reset operation, a current, which flows to the selected word line and the selected bit line, abruptly decreases in turn. Accordingly, a voltage drop due to the parasitic resistance of the wirings almost disappears in turn. As a result, there is a possibility that a voltage, which exceeds the certain voltage necessary for the reset operation and is as high as a set voltage, is applied to the selected memory cell placed in the high resistance state and a so-called erroneous set operation, in which the memory cell is subjected to the set operation by mistake after the completion of the reset operation, may be generated.